Embedded Systems / FPGA Blogs

I’m an FPGA engineer working on high-performance digital design and accelerator architectures. This site contains my notes and blogs on various FPGA tips, techniques and design practices.

Timing Analysis

• FPGA Timing Analysis in Vivado: Setup Slack (Part 1)
• Clock Skew, Uncertainty and Pessimism Removal (Part 2)
• Hold Time Analysis in Vivado: Hold vs Setup Slack (Part 3)
• Reg-to-Pin Timing Analysis (Part 4)
• Pin-to-Reg Timing Analysis (Part 5)

Clock Domain Crossing

• Clock Domain Crossing and Metastability in FPGAs (Part 1)
• The report_cdc Report (Part 2)
• Single-Bit CDC Synchronizers (Part 3)
• Multi-Bit CDC Synchronizers (Part 4)

Embedded Linux (Zynq SoC)

• Embedded Linux on Zynq: Boot Flow and Components (Part 1)
• Embedded Linux (Zynq SoC): Part 2 - Device Tree
• Embedded Linux (Zynq SoC): Part 3 - Device Tree Overlay and UIO
• Writing a Linux Platform Driver for a Zynq PL IP (Part 4)
• Writing a Kernel Driver for a Custom HLS Systolic Matmul IP (Part 5)

On Request

• FPGA Quantization: Rounding, Dither and Saturation
• Fractions in FPGA

— Abdur Rafae Haqqani
rafae50@yahoo.com